Soft errors become a problem in integrated circuits as circuit bandwidths increase. A soft error occurs when particles passing through the integrated circuit deposit enough charge to upset the logic state of the circuit. The susceptibility of high speed circuits to soft errors is due to the very fast nature of the soft error event. The time scale for the deposition of the charge is typically about 50 picoseconds to 3 nanoseconds. Given the very brief event period, slower technologies cannot react to soft errors and are considered insensitive.
Most high speed logic is implemented in current steering logic (CSL). CSL implements Boolean functions by steering a current through differential transistor pairs to develop a differential output voltage across resistive devices, and incorporates current amplifiers, such as source or emitter followers, when increased drive capability is needed. CSL is the basis for silicon emitter-coupled logic (ECL) and current mode logic (CML), gallium arsenide (GaAs) source coupled FET logic (SCFL), some GaAs hetero-structure bipolar transistor (HBT) circuits, and can be found in other semiconductors and associated logic implementations.
Conventional soft error hardening approaches rely upon system level triple modular redundancy coupled with voting logic circuitry. A shortcoming of system level triple modular redundancy is the greater than 300% increase in complexity and power as well as increases in size and weight required in order to provide the hardening function. Furthermore, existing systems which require soft error hardening would typically need extensive redesign for the implementation of system level triple modular redundancy.